1. Field of the Invention
The present invention relates to integrated circuit technology. More particularly, the present invention relates to input/output (I/O) architectures and layouts.
2. The Prior Art
FIG. 1 shows a typical layout for a conventional inline I/O scheme. Pads 10 are used for signals, and pads 12 are used for the power supply and ground supply for the I/O drivers (referred to herein as I/O power and ground supply pads). Persons of ordinary skill in the art will appreciate that there may also be pads for other supplies (not shown) such as for the internal logic, but these are typically less numerous. For every twelve or so I/O signal pads 10, a pair of I/O power and ground supply pads 12 are required to maintain adequate stability on the power and ground supply lines. The exact number of signal pads per supply pad and the exact order of the pads around the perimeter of the chip may vary from that shown based on such considerations as the type of I/O standard supported, the nature of the internal logic on the chip, the fabrication technology, the type of package, or other factors.
Each signal I/O pad is associated with a corresponding I/O cell 14. The I/O cells 14 include the driver circuitry to drive the I/O pad 10, and may also include some electrostatic-discharge protection (ESD) circuitry. Each I/O power and ground pad 12 is also associated with a corresponding cell 16 as well. These cells 16 might include ESD circuitry, bypass capacitors, or other circuitry as is known in the art. The diagrams indicate the desired location of the pads, but the size of the pads may be smaller or larger relative to the size of the cell than is shown.
The pads 10 and 12 in FIG. 1 are shown placed over the active cell circuitry in the corresponding cells 14 and 16, which is currently the preferred implementation. This is not necessarily the case in older technologies, where they may be placed adjacent to the cells along the perimeter of the chip. The pitch, or spacing along the perimeter of the chip, between adjacent pads for this inline layout is labeled Pi. A typical inline pitch might be 47 um, but this may vary depending on the fabrication technology, type of package, or other factors. The effective pitch per signal pad, which includes an amortized portion of the perimeter adjacent to the supply pads, would be (12+2)×47 um/12=54.8 um in this example.
FIG. 2 shows a conventional staggered I/O scheme. By arranging the pads 10 on alternating I/O cells 14 in two staggered rows, the pitch can be reduced. A typical pitch in a scheme such as that shown in FIG. 2 might be 35 um. The area of each I/O cell is about the same as it is in the inline I/O schemes, provided the pads may be placed over active circuitry. (If this is not possible, the cells might be a bit larger.) The number of power-supply pads per signal pad would be about the same as with inline I/O schemes. The effective pitch per signal pad would be (12+2)×35 um/12=40.8 um in this example.
U.S. Pat. No. 6,717,270 discloses a power-ground embedded (PGE) I/O scheme. In this system, bond pads are arranged in a pair configuration. Each pair is part of an I/O cell. The inner pads of a bond pad pair are signal pads for carrying I/O signals to and/or from the die. The outer bond pads are supply pads (either power or ground) for coupling the IC die to either a ground ring or a VDD power ring located on the package substrate. Outer (power supply) bond pads are configured alternately as power pads and ground pads around the IC die periphery.
Utilizing a pad that is selectively couplable to multiple conductive structures in a two pad I/O cell may provide for a die with greater utilization of die space, thereby allowing for the possibility of more I/O cells per IC die. In some instances, one pad may be coupled to a signal and the second pad may be selectively coupled to either a power or ground conductor, thereby allowing for a single I/O pad cell which incorporates either a power or ground pad to maximize flexibility for power and ground placement in a bank of I/O cells. The effective pitch of the signal I/O cells is reduced because separate power-supply cells are no longer required. For example, if the typical inline pitch of 47 um is used between adjacent I/O cells, the effective pitch is exactly the same, 47 um. This compares favorably with the effective pitch of 54.8 um for the conventional inline scheme of FIG. 1. Also, there are many more supply pads per signal pad (a 1:1 ratio for the PGE scheme vs. a 2:12 ratio for the conventional schemes). This contributes to providing a more stable voltage level on the supply lines on the chip than is possible with the conventional schemes. However the effective pitch is worse than that of a conventional staggered I/O scheme like that of FIG. 2 in that not as many I/Os fit around a chip of a given perimeter. This may be seen from an examination of the TABLE below.
In the example set forth in the TABLE, it is assumed that for every 12 signal pads provided, one power supply and one ground supply pad will be necessary. This makes a total of 2 supply pads for every 12 signal pads. (To keep the comparison simple any additional supply pads required for internal logic, etc. are ignored) Normally each supply pad needs its own I/O cell. With PGE, these separate power-supply and ground-supply pads are eliminated by embedding a power-supply pad or ground-supply into each signal I/O cell.
TABLESeparateEmbeddedEffectiveTotal SupplySignalSupplySupplyPitch perPads per SchemePadsPadsPadsTotal Perimeter RequiredSignal PadSignal PadInline122047 × 14 = 65854.8 2/12Staggered122035 × 14 = 49040.8 2/12PGE1201247 × 12 = 5644712/12Staggered120647 × 3 × (12/4) = 42335.3 6/12Group(FIG. 4)Staggered1206(2 × 35 + 2 × 47) × (12/4) = 49241.0 6/12Group(FIG. 5)
Because the PGE scheme already uses two rows of pads, one for signals and one for supplies, it does not lend itself to staggering pads. Adding a third or fourth row of pads would require another vertical layer of bonding wires, and additional complexity in the integrated circuit package.